FIG. 1 is an explanatory diagram illustrating a configuration example of an amplifying circuit. The amplifying circuit includes an n-channel field-effect transistor (FET) 101 for amplifying an input signal supplied from a signal source 100. The input signal from the signal source 100 is first passed through a resistor R10 and then fed into a capacitor C10 where the DC component of the input signal is removed. The input signal whose DC component is thus removed, and then summed with a gate bias voltage, and the resulting signal is applied to the gate terminal of the FET 101. The gate bias voltage is supplied from a power supply line that supplies predetermined voltage Vg via a resistor R11, which is grounded via a capacitor C11.
The drain terminal of the FET 101 is coupled via an inductor L10 to a power supply line that supplies voltage Vd. This power supply line is grounded via a capacitor C12. The amplified signal obtained by amplifying the input signal by the FET 101 is output from its drain terminal and applied via a DC component removing capacitor C13 to a load 102.
The gate voltage biasing method of the FET 101 includes a class of operation intended for power conservation, which is described as class B operation, class C operation, etc., according to the magnitude of the voltage applied to the gate. The biasing method further includes a class of operation described as class AB operation in which bias current flows even during a period when there is no input signal in order to avoid signal waveform distortion that occurs near the pinch-off voltage, though this operation increases power consumption compared with the above two classes.
There is proposed a class AB operating transistor power amplifying circuit for amplifying an amplitude-modulated wave, which includes a detector for detecting a portion of an input signal, an impedance conversion circuit for performing impedance conversion on the output of the detector, a time constant circuit for integrating the output of the impedance conversion circuit, and an amplifying circuit for amplifying the output of the time constant circuit. The base bias of this transistor power amplifying circuit is controlled by the output of the amplifying circuit.
There is also proposed a power amplifier wherein when amplifying an input power signal by a class B or class AB amplifier, the gate voltage can be set to the operating point of FET without an operator having to make an adjustment for setting the gate voltage to the operating point. This power amplifier includes a first field-effect transistor which amplifies the input power signal applied to its gate terminal and outputs the amplified signal at its drain terminal, a bias setting circuit which applies a predetermined voltage to the gate terminal while maintaining a first drain current applied to the drain terminal at a predetermined value, a detector circuit which produces a voltage signal proportional to the magnitude of the input power signal and sends it out from an output terminal, and a current supply circuit which supplies the drain terminal with a second drain current corresponding to the voltage signal received from the detector circuit.
Related art is disclosed in Japanese Laid-open Patent Publication No. H03-249810 and Japanese Laid-open Patent Publication No. 2004-274316.